1. Field of the Invention
The invention relates generally to memory cells, and more particularly, to Dynamic Random Access Memory (DRAM) cells having bar-shaped storage node contact plugs and methods of fabricating the same.
2. Description of the Related Art
Generally, a semiconductor device having DRAM cells includes at least a cell in a cell array region. The cell includes a capacitor and a transistor, which are formed on an active region. The capacitor is formed of an upper electrode layer, a dielectric layer, and a lower electrode layer, and each of the lower and upper electrode layers comes in contact with a conductive layer. At this time, the conductive layer connected with the lower electrode layer is a doped polysilicon layer, and the conductive layer connected with the upper electrode layer may be formed of a metal layer. The conductive layer that is connected with the upper electrode layer can be significantly manipulated without impacting a design rule of the semiconductor device, unlike the conductive layer that is connected with the lower electrode layer.
However, the more that the design rule for the semiconductor device is reduced, the chance is greater that the conductive layer connected with the lower electrode layer is effected. The conductive layer connected with the lower electrode layer could partially overcome contravention of the reduced design rule, as the capacitor structure of the semiconductor device changes from a CUB (Capacitor Under Bit-line) structure into a COB (Capacitor Over Bit-line) structure.
Also, as semiconductor devices become increasingly integrated, certain features of the semiconductor device become increasingly important. These features include spaces between conductive layers connected with lower electrode layers on the cell array region, a diameter of a contact window connecting the lower electrode layer with the conductive layer, and the doping concentration for one or more layers that form the conductive layers.
Many schemes for increasing the diameter of the contact window while maintaining the reduced design rule have been proposed. That is, the contact regions may be enlarged by forming the contact window that connects the lower electrode layer with the conductive layer through a new semiconductor fabrication process that is different from existing semiconductor fabrication processes, or by modifying shapes of the lower electrode layer and the conductive layers. Accordingly, these schemes may be carried out by using the reduced design rule and the new semiconductor fabrication process without upgrading the semiconductor fabrication equipment.
On the other hand, U.S. Pat. No. 6,136,643 to Erik S. Jeng (the '643 patent) discloses a method of fabricating dynamic random access memory having a COB structure. According to the '643 patent, the method includes forming a DRAM cell having the capacitors of the COB structure as well as active regions, gate patterns, and bit line patterns. The method also includes forming openings in predetermined regions between the bit line patterns. The openings penetrate a third sacrificial insulating layer by using dual photo and etching processes. At this time, capacitor contact nodes that are formed on the active regions are exposed. Although sidewalls of the bit line patterns are covered with a third etch stop layer before the openings are formed, the sidewalls of the bit line patterns can be exposed because the dual etching processes cause excessive etching damage to the third etch stop layer. Thus, the lower electrode may be electrically shorted to the bit line patterns through the openings.
Embodiments of the invention address these and other disadvantages of the conventional art.